The realization method of PS/2 keyboard interface based on programmable logic device

As one of the most commonly used human-machine interface devices in embedded systems, keyboards are widely used in embedded systems. However, developers generally use self-designed simple matrix keyboards. This type of keyboard is only a matrix switch arranged in rows and columns, and often needs to be designed and made separately, and its versatility is not strong. When more keys are needed, more I/O ports will be occupied. In the software, power-on reset key scanning and communication processing are required, and the de-jitter processing of the keys must be added, which increases the system’s Software and hardware overhead.The PS/2 keyboard has a built-in design that automatically removes key jitter, and automatically recognizes key presses and

As one of the most commonly used human-machine interface devices in embedded systems, keyboards are widely used in embedded systems. However, developers generally use self-designed simple matrix keyboards. This type of keyboard is only a matrix switch arranged in rows and columns, and often needs to be designed and made separately, and its versatility is not strong. When more keys are needed, more I/O ports will be occupied. In the software, power-on reset key scanning and communication processing are required, and the de-jitter processing of the keys must be added, which increases the system’s Software and hardware overhead. The PS/2 keyboard has a built-in design that automatically removes key jitter, and automatically recognizes the pressing and release of keys. The software and hardware can be easily developed, cheap, stable and reliable. The PS/2 keyboard has been used as the input device of the embedded system. Become a feasible solution. At present, most of the applications of PS/2 keyboard control are controlled by single-chip microcomputers. Compared with single-chip microcomputers, FPGA has the characteristics of more flexibility, higher integration, and easy transplantation than single-chip microcomputers.

Based on the analysis of the PS/2 protocol and the working principle and characteristics of the PS/2 keyboard, this paper presents the implementation method of the PS/2 keyboard interface on the ALTERAFLEX10K.

1 PS/2 interface protocol

1.1 PS/2 physical characteristics

The PS/2 device interface is used in many modern mice and keyboards. It was originally developed by IBM. The most common is the 6-pin mini-DIN. The pin structure and appearance are shown in Figure 1.

The realization method of PS/2 keyboard interface based on programmable logic device

PS/2 devices are divided into master and slave, and the widely used PS/2 keyboards and mice all work in slave device mode. The clock and data lines of the PS/2 interface are both open-collector structures and must be connected with a pull-up resistor. Generally, the pull-up resistor is set in the master device. The data communication between the master and slave devices is transmitted in a two-way synchronous manner. The clock signal is generally transmitted by Generated from the device.

1.2 The structure of the data packet Each time the state of the keyboard changes, the keyboard will send out at least a three-byte data packet. When a key is pressed, it will send the key’s make code (Make Code) to the host, and when the key is released, it will send a break. Code (Break Code). For example: the pass code of the key “A” is 0x1C, and the break code of the key “A” is: 0xF0, 0x1C, so when the key “A” is to be transmitted, the code of the data packet sent by the keyboard is: 0x1C, 0xF0, 0x1C.

1.3 Timing logic of the interface

PS/2 protocol is a two-way half-duplex serial communication protocol. The clock signal is generated by the keyboard. The maximum clock frequency is 33kHz, and the recommended frequency is 15kHz. Both ends of the communication are synchronized through Clock, and data is exchanged through Data. If either party wants to prohibit the other party from communicating, they only need to pull the Clock to low level. The transmission sequence is divided into two different sequence logics of sending and receiving according to the different transmission directions. Figure 2 is a sequence diagram from the keyboard to the host.

The realization method of PS/2 keyboard interface based on programmable logic device

Among them: Start: start bit, always ‘0’ (low level)

Data0~Data7: 8-bit data bits (low bit in front, high bit in the back)

Parity: Parity bit (odd parity)

Stop: stop bit, always ‘1’ (high level)

When the keyboard wants to communicate with the host, the keyboard always first checks whether the clock line is high, if not, it means the host is communicating, and the data to be sent must be buffered until the control of the bus is regained (the keyboard has 16 bytes Buffer), that is, wait until the clock line is high before sending data. And the data from the keyboard to the host can only be read on the falling edge of the clock.

When the host communicates with the keyboard, the host will first set the clock line and data line to the “request to send” state. The specific method is as follows: first pull down the clock line for at least 100 μs to inhibit communication, then pull down the data line to “request to send”, and finally release the clock. During this process, the keyboard will check this state within an interval of no more than 10 μs. When the keyboard checks this state, it starts to generate a clock. It is different from the data reading method sent by the keyboard, the data sent by the host must be read on the rising edge of the clock.

2 The design and realization of PS/2 interface

2.1 Logic simulation

This design adopts a top-down module design method, considering the need to design the following modules: serial-to-parallel conversion module, sorting receiving module, control module, package sending module, etc. The logical relationship of these parts is shown in Figure 3:

The realization method of PS/2 keyboard interface based on programmable logic device

The serial-to-parallel conversion module mainly receives and sends transmission data, and can convert serial data into the required parallel data. The function of the sorting receiving module is to sort and extract the data packets from the serial-to-parallel conversion module according to certain requirements, so as to obtain useful information. The control module is the core of the design, and the PS/2 interface is a half-duplex serial bus, so its sending and receiving cannot be carried out at the same time, and the control module needs to strictly control its timing. The control module is responsible for coordinating the whole process of the whole design, and the design idea of ​​state machine is adopted in this design. The package sending module is similar to the sorting receiving module, except that the command data to be transmitted is converted into the format of the sending data packet required by the PS/2 protocol. The flow chart of the entire design is shown in Figure 4:

The realization method of PS/2 keyboard interface based on programmable logic device

When the system is powered on or reset, the master device first sends an initialization signal to the keyboard. After getting the keyboard’s response signal, the system enters the bus idle state and can send and receive data, but the master device has a higher priority. If a sending request is received while in the receiving state, the data reception will be interrupted and the data sending state will be directly entered.

Use MAX+plusⅡ 10.2 to carry on the software simulation to the design, according to the modular design idea to carry on the simulation to each module separately. Figure 5 is a simulation timing diagram of the receiving data module.

The realization method of PS/2 keyboard interface based on programmable logic device

2.2 Hardware verification

The hardware verification is implemented in the GW-48 experiment box. The reset circuit, power supply circuit, FPGA chip, program download circuit, PS/2 interface circuit, digital Display circuit, etc. are used in the system.

Select FLEX10K series EPF10K10LC84-3 FPGA device for synthesis. After downloading the synthesized configuration file to the development board, the system is powered on, the PS/2 device is initialized and the keyboard input is correctly observed in the experiment box.

3. Concluding remarks

FPGA hardware verification shows that each module of the design successfully realized the data transfer process after reset and reached the expected goal. The versatility of the VHDL language determines its strong portability, and it has a certain reference value for practical applications.

The author of this article is innovative: the research done in this article is based on the use of a single-chip microcomputer to realize the PS/2 interface, and re-use FPGA to realize the control of the PS/2 interface. Compared with the traditional single-chip implementation method, this method has the characteristics of simple implementation, strong portability, and easy integration. This method has good promotion value.

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