Kernels: How post-Moore decline plays a role


Chip has gradually become one of the hot words in the semiconductor industry. It is considered to be an effective solution that can delay the failure of Moore’s Law, slow down the process time, and support the continued development of the semiconductor industry.

Evolution of Moore’s Law

Even if you are not an IT practitioner, you must have heard of the famous “Moore’s Law”: In 1965, Intel founder Gordon Moore proposed that the integration level of integrated circuits would double every two years for at most ten years, and later This cycle was shortened to 18 months. At that time, Mr. Moore only limited the application time of Moore’s Law to “10 years”, but in fact the development of processor technology is staggering, and this wonderful law, which was questioned by countless people at that time, is still in effect. The two-year process technology will enter a new level.

However, now the mainstream processor process has developed to 22nm, and the more advanced 14nm and 10nm processes have also entered the product blueprint of chip manufacturers. The size of silicon wafer transistors has its physical limit, said Robert Robert, director of the US Defense Advanced Research Projects Agency. Mr. Colwell once said that with the continuous development of semiconductor technology, the manufacturing process has reached 7nm, and it is impossible to meet the requirements of performance, power consumption, area and signal transmission speed at the same time by reducing the line width. More and more semiconductor manufacturers have begun to pay attention to Focusing on the system integration level, it is urgent to discover new materials and chip technologies to become substitutes for silicon transistor technology. However, this is beyond Moore’s Law. It is achieved through system integration of a single chip or multi-chip stacking, hoping to achieve more functions.

The technology star of the post-Moore era – core particles

In recent years, semiconductor manufacturers have found that chips can be considered as an effective solution to delay the failure of Moore’s Law, slow down the process time, and support the continued development of the semiconductor industry. So what are core particles? Theoretically, the core mode is a method with short development cycle and low cost, which provides the flexibility of advanced technology and mainstream mature process selection. Core technology is like building blocks, which can combine different node processes (10nm , 14/16nm and 22nm), different materials (silicon, gallium arsenide, silicon carbide, gallium nitride), different functions (CPU, GPU, FPGA, RF, I/O, memory), chips from different semiconductor companies are packaged in Together.

The advantages of preservative core particles in the post-Moore era

The “redirection” of monolithic integration to multi-chip heterogeneous packaging integration technology in the post-Moore era is an important trend. Compared with the previous soft IP form, the chip is a silicon-proven bare chip. Chips can provide higher bandwidth, lower power, lower cost, and more flexible form factors while enabling high-performance computing.

At present, many companies have created their own chip ecosystems. With the chip process from 10nm to 7nm, 5nm to the future 3nm, the cost and development time required for each process reduction are greatly increased. Moreover, when the chip process is close to 1nm, it will enter the world of quantum physics, and the existing process will be greatly affected by quantum effects.

In the future, the chip integrated in the chip mode will be a “super” heterogeneous system, bringing more flexibility and new opportunities to the IC industry.

The advantages of preservative core particles in the post-Moore era

The key to the success of the core mode is the standard and interface of the core. But as an innovation, the core particle model has multiple challenges.

① Technical level

There is no uniform standard for the assembly or packaging of die. At present, major players have their own solutions. Although they have different names, they are inseparable from through silicon vias, silicon bridges and high-density FO technologies. Whether it is die stacking or large-area splicing, interconnection is required. Lines will become shorter, requiring interconnects to be 100% defect-free or the entire chip will not work.

② Quality assurance issues

Compared with traditional soft IP, die is a silicon-proven bare chip, which can ensure the correctness of physical implementation. But if there is a problem with one of the bare chips, the entire system is affected, at a high cost. Therefore, it is necessary to ensure that the core particles are 100% trouble-free. Of course, this also includes post-integration testing. After packaging, some chips may not be directly accessible from the external pins of the chip, which brings new challenges to chip testing.

③ Heat dissipation problem

Several or even dozens of bare chips are packaged in a limited space, and the interconnect lines are very short, making the problem of heat dissipation even more difficult.

④ Chip network problem

Although each chip itself is designed not to deadlock and its communication system works well, when they are all connected together to form a chip network, traffic deadlock and traffic congestion can occur. AMD researchers recently proposed a solution to the deadlock problem. If the deadlock problem can be completely solved, then the chip will bring new impetus to the development of future computer design.

⑤ The problem of supply chain reshaping

Under the chip mode, EDA tool providers, chip providers, and packaging and testing providers have to change. For example, the problems in the chip mode may ultimately need to be answered through the improvement of EDA tools, which requires EDA tools to provide comprehensive support from architecture exploration, chip implementation, and even physical design. There is also the issue of synchronizing the progress of bare chips from different chip suppliers entering the packaging supplier factories.


Chips will drive the future of the semiconductor industry, and this is an upcoming MCP tsunami. Large-scale chip manufacturers are also turning to chips. Whether an open industrial ecology will be formed in a few years and whether to establish a chip ecological promotion alliance are questions worthy of consideration by the industry.

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