“Digital tuning system is the core of modern transceiver, its performance directly affects the quality of communication, its main part is the integrated phase-locked frequency synthesizer. The integrated phase-locked loop is combined with the microprocessor, which can be controlled by the microprocessor to complete all the functions of the frequency synthesizer.
Authors: Wang Renfa; Lin Zhisheng; Lu Nanchang; Xiong Yan
Digital tuning system is the core of modern transceiver, its performance directly affects the quality of communication, its main part is the integrated phase-locked frequency synthesizer. The integrated phase-locked loop is combined with the microprocessor, which can be controlled by the microprocessor to complete all the functions of the frequency synthesizer.
In this paper, a new bicyclic scheme that is completely different from the conventional bicyclic scheme is realized. This scheme uses a higher phase detection frequency and adopts a direct digital synthesis (DDS) chip. By changing the clock frequency and frequency control word of the DDS, the reference phase detection frequency has a small change, and the output frequency of the loop can be changed. To achieve the purpose of precise frequency synthesis. The scheme not only solves the contradiction between small channel spacing and high spectral purity, but also has high conversion speed; the calculation and control are completed by a single-chip microcomputer.
1 Principle of the new scheme
The simplified schematic diagram of the system is shown in Figure 1. Among them, the B loop makes the output frequency f0 of the tuner change greatly, and the A loop provides the clock frequency fc for the DDS chip. As long as the total frequency division ratio NA of the A loop and the frequency control word of the DDS are changed, the DDS output frequency fd makes a small change, then The f0 can be changed in steps with a smaller interval frequency.
Figure 1 Schematic diagram of the scheme
Assuming that the phase detection frequencies in the A and B loops are 100kHz and 300kHz respectively (obtained by the crystal oscillator and fd respectively through the reference frequency divider), the total frequency division ratios of the dual-mode frequency division and the program frequency division in the frequency synthesis chip are NA and NB, f0=1700MHz “1850MHz, f′0=850MHz” 925MHz, △f0=25kHz, then △fd=4.16Hz～4.41Hz is obtained from the frequency relationship when the loop is locked; so as long as △fd≤4.41Hz, it can be The frequency resolution of the output is 25kHz. Generally, the output frequency interval of DDS is less than 0.1Hz, which can meet this requirement. Similarly, when △f0=±150kHz (for every 1 change of NB, f0 changes by 300kHz), △fd=±(25～26.47) Hz, as long as the maximum change of fd is ±26.47Hz, △f0 can cover 300kHz. The above shows that after using DDS, the two loops can be completely used with high phase detection frequency, which can greatly improve the frequency conversion rate.
The DDS used in the above scheme is a sampling system, and there are phase rounding errors, amplitude quantization errors, errors caused by the nonlinearity of the DAC, etc., so its output is a composite signal spectrum, including the DDS output frequency fd, clock frequency fc and Its various harmonics, various combined frequencies, and other spurious signals. According to the derivation in the literature, the output frequency ω of the actual DDS is:
B is the low number of bits rounded from the phase accumulator N, K is the frequency control word; mωp is the spur generated by the phase rounding, nωc is the harmonics of the clock, and lωd is the harmonics of the output.
Among them, the amplitude of the fc-fd spurious component is the largest, that is, the spurious suppression of the output signal is determined by the amplitude of the fc-fd and the out-of-band suppression of the LPF. If the frequency interval between fd and fc-fd is larger, the amplitude difference between the main frequency and the clutter will be larger, so that the influence of the clutter on the DDS can be reduced. The frequency of the general crystal oscillator is not very high, but the desired frequency can be obtained by using the phase-locked loop (A loop) to increase the frequency interval between the main frequency and the clutter.
In addition, in the formula (1), the first term is caused by the phase truncation, and this spur can be reduced by selecting an appropriate clock frequency and frequency control word. It can be seen from the formula (2) that when K-int (K/2B)·2B=0, ωp=0, the phase truncation will not make the output spectrum of DDS produce spurious. Therefore, a phase-locked loop (A loop) can be used to provide a clock signal for the DDS. Since the A-loop is a phase-locked loop, the clock frequency of the DDS is variable, and the spurious can be suppressed by adjusting the clock of the DDS, and the output frequency of the DDS can also be changed by changing it, thereby changing the entire output frequency. The function of frequency hopping can also be realized through software programming.
2 The realization of the circuit
The whole circuit is divided into five parts: A ring, DDS unit, B ring, two frequency division unit and single chip control unit.
2.1 Design of DDS circuit
DDS selects AD9850 of AD Company. Its frequency control word K consists of N-bit binary numbers, and the output frequency is determined by the frequency control word:
According to the sampling law, the maximum output frequency of DDS should be less than fc/2, and it can only reach 0.4fc in practical applications.
The clock of DDS selects the output of ring A, and the frequency range is 80MHz “100MHz. The highest clock of DDS is 120MHz, so it meets the clock requirements. The output frequency range of DDS is 15MHz” 19MHz, the center frequency is 17MHz, and the frequency change range can be less than 0.02Hz , fully meet the signal requirements of the output frequency interval of 25kHz. A bandpass filter is used to suppress spurs and noise from the DDS output.
2.2 Ring A
It is mainly composed of integrated chip MC145170 plus loop filter (LF), voltage controlled oscillator (VCO), temperature compensated crystal oscillator (TXCO) and amplifier.
(1) Phase-locked loop chip MC145170
The chip mainly includes programmable ÷R, ÷N frequency divider, 8-bit program control C register, single-ended phase detector PDA and double-ended phase detector PDB and lock indicator LD. Different reference reference frequencies fr can be obtained by selecting different external reference sources or changing the reference frequency division ratio R; fv can be obtained by changing the value of the program frequency division ratio N; the C register is used to control the work of the entire chip; the lock detector LD Used to detect and indicate if the loop is locked. The single-ended phase detector PDA is a three-state single-ended output. When fv>fr or the phase of fv is ahead, it outputs a negative pulse; on the contrary, it outputs a positive pulse; when fv=fr and the same phase, the output is in a high-impedance state. The double-ended phase detector PDB is a double-ended output, which can form a loop error signal externally. When fv=fr or the phase of fv is ahead, ΦV outputs a negative pulse; on the contrary, ΦR outputs a negative pulse; when fv=fr and the same phase, except for a very short, same-phase negative pulse, both remain high. flat.
(2) Voltage Controlled Oscillator VCO
VCO selects MAX2606, the circuit is shown in Figure 2. It is a miniature, high-performance IF VCO. The frequency range is 70MHz to 150MHz, and only a small amount of peripheral components are needed. The most important thing to pay attention to is the choice of the external Inductor LF, which is used to adjust the VCO output frequency. I choose the inductor LF=454nH to obtain 80MHz” 100MHz frequency output. When changing this inductance, the output frequency range also changes. In addition, the choice of the capacitor C2 connected to the output terminal is also very important. If C2 is too large, it cannot match the internal circuitry of the MAX2606, causing the entire loop to fail.
(3) A-loop loop filter LF
The loop adopts the phase detector PDA in MC145170, and an external loop filter is connected to its output PDOUT. The loop filter uses a passive proportional-integral filter, as shown in Figure 3. The parameters of the filter are determined by equations (4) and (5).
Among them, ωn is the equivalent natural frequency of the loop, ξ is the equivalent damping coefficient, KΦ is the phase detection sensitivity of the phase detector, KVCO is the voltage control sensitivity of the VCO, and N is the total frequency division ratio of the feedback loop. In general, ξ takes 0.707 to 1, and ωn takes the above formula to calculate the parameters.
(4) A-ring output amplifier
Select the integrated chip MAX2611. The MAX2611 is a low-noise amplifier with high drive capability from DC to 1100MHz with a gain of 18dB at 500MHz.
It is mainly composed of integrated chip MC145201 plus loop filter, voltage-controlled oscillator and amplifier; MC145201 is similar to MC145170.
(1) B-loop loop filter LF
Using the single-ended output of MC145201, the loop filter is composed of R and C. The structure and parameters can refer to the design of the loop filter of A loop.
(2) B-ring amplifier
Using the MAX2473 chip, it is a wideband, high reverse isolation buffer amplifier. Use it to isolate the impact of the load on the VCO, while increasing the power of the VCO output signal to drive the divider by two.
(3) The final output frequency range of ring B is 1700MHz “1850MHz
2.4 Divider by two
Using an active two-frequency divider chip (MF220), the output frequency of the B-ring is divided into two to obtain a frequency of 850MHz to 925MHz.
3 Experimental results
(1) The experimental pictures (note: the resolution of 1kHz is the highest resolution of the spectrum analyzer) are shown in Figures 4 to 7.
It can be seen that a good output spectrum and a good output waveform can be obtained after the loop is locked.
(2) The frequency stability measurement results are shown in Table 1.
The conclusion of the general phase-locking theoretical analysis is: when the loop is locked, the frequency stability of the loop output and the frequency stability of the reference source are of the same order of magnitude.It can be seen that the actual measurement results are in good agreement with the theoretical analysis.
Frequency stability (30min time period)
A ring output
Table 1 Frequency Stability Measurement Results
Figure 5 Spectrogram of DDS output when ring A is used as clock
Figure 8 Spectrogram at 200 hops/s
4 Frequency hopping output effect
The two main indicators of a frequency hopping system are the frequency hopping bandwidth and the frequency hopping rate. Generally speaking, it is hoped that the frequency hopping bandwidth should be wider, the number of frequency hopping frequencies should be larger, and the frequency hopping rate should be faster. The frequency hopping speed of the system can reach at least 5000 hops/s. Figure 8 is a picture at 200 hops/s. Due to the limitation of equipment, pictures with higher frequency hopping speed cannot be taken. However, it can be judged whether the lock is lost during high-speed frequency hopping by monitoring the lock indication signal of the phase detector.
The scheme of this system largely solves the contradiction among the phase detection frequency, frequency interval and spectral purity in the phase-locked loop, realizes the rapid frequency jump and small step, and has a higher frequency output. It can be seen from the above experimental pictures and data that the digital tuning system composed of the new DDS+ double phase-locked loop frequency synthesizer has excellent performance.