Application Scheme of Realizing Embedded Ethernet Interface Based on STR710 Processor

With the rapid development of the network. The application of embedded system is becoming more and more widespread. Not only PCs can access the Internet, but also all kinds of embedded devices can access the Internet. Embedded devices that can access the Internet need to add the TCP/IP network protocol, which also puts forward higher requirements for the equipment that detects the operating status of the power system. . Embedded systems have been widely used in various fields due to their small core, strong specificity, simplified system, and high real-time performance. Therefore, the networking of embedded devices is the trend of technological development so far.

Author: Wang Guiyun, Hou Sizu

1 Introduction

With the rapid development of the network. The application of embedded system is becoming more and more widespread. Not only PCs can access the Internet, but also all kinds of embedded devices can access the Internet. Embedded devices that can access the Internet need to add the TCP/IP network protocol, which also puts forward higher requirements for the equipment that detects the operating status of the power system. . Embedded systems have been widely used in various fields due to their small core, strong specificity, simplified system, and high real-time performance. Therefore, the networking of embedded devices is the trend of technological development so far.

In today’s economy and society, the power load is increasing rapidly, and the pollution of harmonics to the power system is getting more and more serious, and it is the most important indicator that affects the target power grid. This article is based on a case study of an ARM-based voltage harmonic intelligent monitoring and harmonic elimination device, focusing on the design and implementation of the embedded Ethernet interface of the STR710 processor based on the ARM7 core.

2 The structure block diagram and working principle of voltage harmonic intelligent monitoring and harmonic elimination equipment based on ARM

The main structure of this device includes: switching power supply module, signal sampling and conditioning circuit, A/D conversion circuit, real-time clock circuit, data storage circuit, network port circuit, human-computer interaction Display circuit and ARM7 controller. The system structure block diagram is shown as in Fig. 1.


Figure 1 Structural block diagram (strueture)

The two measured signals are collected by voltage transformers, and then converted into digital signals in the required range by signal conditioning and A/D converter, and then sent to ARM7 for processing. ARM chip can use FFT to calculate the effective value of each voltage and the content of 2nd to 32nd harmonic, and then refer to the grid voltage harmonic standard for corresponding processing. If it is a high-order harmonic, the triac will be triggered immediately, and the trigger signal can be cancelled when it is cut off. The switch turns off by itself after the current crosses zero. In this way, ARM7 can effectively control the conduction and conduction time of the thyristor and eliminate harmful harmonics.

The collection of voltage signals is critical to the accurate measurement of any power quality parameters of the grid frequency. A precision voltage transformer is used in the monitor to convert the input signal into a milliampere-level current signal, and the voltage signal is obtained through the resistance. The signal conditioning circuit is composed of a voltage follower circuit, a full-wave rectifier, a phase-locked loop circuit and a frequency divider circuit. Among them, the phase-locked loop circuit and the frequency divider circuit keep the signal synchronization in order to accurately measure the harmonics. Since this monitor is sufficient to monitor two channels of signals, each channel needs to sample 256 points of data within 20ms, which has higher requirements on the speed of the A/D chip. The monitor A/D conversion chip uses AD7492 with a maximum sampling frequency of 750kHz.

The harmonic elimination device mainly uses bidirectional silicon controlled components to directly act on the open delta winding of the voltage transformer. The communication part mainly has 232, 485 and network port forms. The voltage harmonic calculation is completed by the ARM chip using the FFT algorithm. The ARM7 chip used in this article is ST’s STR710. The design and realization of ARM7 Ethernet interface adopts STR710 microcontroller and Ethernet control chip CS8900A for hardware design, and communicates through TCP/UDP protocol.

The ARM7 chip can realize lively online monitoring and elimination through the design and implementation of the Ethernet interface with the CS8900A controller. It is of great significance to the maintenance of the power system.

3 Introduction to STR710

STR710 is a microcontroller based on 16/32-bit ARM7TDMI. STR710 features include: support for 32-bit/16-bit RISC architecture (ARM v4T). On-chip integrated flash and RAM memory up to 64KB. Has 4 external memory interfaces (EMI). 32-bit ARM instruction set and 16-bit Thumb instruction set. Has non-multiplexed 16-bit data and 24-bit address bus. STR710 integrates many standard interfaces, including USB-Device, 4 UARTs, 10Base-T Ethernet controller and so on. STR710 also integrates the debugging functions of JTAG-ICE and UART debugging channel (DBUG).

4 CS8900A Ethernet Controller

The CS8900A Ethernet controller is a low-cost Ethernet control chip from Cirrus Logic, which integrates the IEEE802.3 protocol standard media access control sublayer (MAC), and supports full-duplex operation. In addition to the basic functions of other Ethernet controller chips, it also has its own unique advantages: optimized in the industry standard architecture (ISA); the unique PacketPage structure can automatically adapt to changes in the network communication mode, occupying less system resources, thus Increase system efficiency; highly integrated design, suitable as a network interface for intelligent embedded devices.Design in this article

This design uses the Ethernet interface scheme composed of STR710 and CS8900A. The software and hardware system structure is shown in Figure 2:


Figure 2 System structure diagram (figure2: system structure)

5 Hardware circuit

Combining the respective characteristics of the STR710 microprocessor and CS8900A, the hardware schematic diagram of the embedded Ethernet interface is shown in Figure 3.

(1) The read signal (IOR not) of the CS8900A end is connected to the read signal (RD) of the STR710 and the off-chip memory CS1 (bank1) through the OR gate (74HC32).

(2) The write signal (lOW NOT) of the CS8900A end is connected to the write signal (WEO) of the STR710 and the off-chip memory CS1 (bank1) through the OR gate (74HC32).

(3) The data buses D0-D15 are connected correspondingly for 16-bit data transmission.

(4) CS8900A address bus (SA1-SA3) is connected to STR710 (A12-A14), CS8900A address bus SA0 and system bus enable (SBHE non) are connected to STR710 address bus A11.

(5) The reset signal is connected correspondingly.


Figure 3 Hardware connection principle (figure3.hardware connection principle)

6 Software implementation

6.1 Program design of driver module CS8900

What this text adopts is the I/O mode of CS8900A. The CS8900 driver module program includes the following:

(1) Set the Ethernet physical address, which can be modified before the CS8900 is initialized. (2) Define the received frame type, Ethernet data. The address port (3) sets the working mode, 8-bit or 16-bit mode. This design adopts 16-bit mode. In this article, both SBHE and SA0 in CS8900 are connected with the address bus A11 of STR710 to make it work in 16-bit mode. Set the register and interrupt mode used in the process of sending and receiving data packets. (4) Send frame request. Initialize the CS8900. Data packet sending and receiving process.

Since the CS8900A address line SA0 is connected to the STR710 address bus A11 (see the schematic diagram in Figure 3), the port address to access the CS8900A must be shifted by 11 bits to the left. The address range of the off-chip memory Bank1 is 0x62000000-0x62FFFFFF. That is, the first address is 0x62000000. The Ethernet port address related program can be defined as:

#define ETH_Port(n)(*(vu 16*)(0x62000000 I(n)《》11)) The software flow chart of initializing CS8900 is shown in Figure 4:


Figure 4 Software flow chart (software flow chart)

6.2 Implementation of LwIP protocol stack

LwIP stands for Light Weight IP protocol. It is an open source TCP/IP protocol stack for embedded systems developed by Adam Dunkels of the Swiss Computer Institute (SICS) and others. It takes up little space. On the basis of protecting the main functions of the protocol, it reduces the occupation of RAM and ROM. Generally, it only needs tens of K of RAM and about 40K of ROM to run. LwlP implements relatively complete IP, CMP, UDP, and TCP protocols. It has the functions of timeout estimation, fast recovery and retransmission, window adjustment and so on. The protocol stack provides a set of API functions to be called by the application program, which is convenient for programming. Due to the flexible data packet storage mechanism. The data sent and received does not need to be copied between the various layers of the protocol, and the memory consumption is small.

The realization of the UDP protocol in the design of this article includes the following content: (1) Set the communication UDP IP address and port, set the sending buffer type (2) Set the UDP function function, allocate a new UDP PCB, and allocate memory for the buffer ( 3) CS8900A reset (4) Initialize the internal buffer and network interface of LwIP, set the MAC address (5) Modify the default network configuration to meet specific needs. Configure the network address. Gateway, subnet mask (6) Establish the LwlP network interface, set it as the default network interface and start the network interface (7) Initialize IP, TCP, HTTP module (8) UDP port binding, specify the receiving callback function, and receive the information from the NIC Data packet, is there any data packet accepted? If there is. Hand over the data packet to LwlP for processing.

7 concluding remarks

With the rapid development of economy and technology, the non-linear load of many household appliances such as electric arc furnaces has been increasing, resulting in an increase in the level of harmonics in the power system. Therefore, the over-current and over-voltage caused by the system resonance caused by the harmonics can not be ignored, and the harm to the safe operation of the power system cannot be ignored. Through the case study of the ARM-based electric leg harmonic intelligent monitoring and resonance elimination device , Is of great significance to the safe operation of the power system.

The author of this article is innovative: Propose an implementation method based on ARM7 embedded Ethernet interface under transplanting LwlP protocol stack. And successfully used for implementation on the ARM7 development board. At present, the ARM processor has become the most widely used embedded processor due to its high performance, low cost, and low power consumption, and the CS8900A Ethernet controller has excellent performance. Low power consumption, low price waiting point. It occupies a large proportion of 10Mb/s embedded network applications in the market. Therefore, the research of ARM-based voltage harmonic intelligent monitoring and harmonic elimination devices, especially the realization of ARM7 embedded Ethernet interface, is useful for prevention and suppression. The slowing down of harmonic resonance is bound to have a good application prospect.

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