【Introduction】In “Development of 25 kW Fast DC Charging Pile Based on Silicon Carbide”[1-3] In this new article in the series, we focus on the DC-DC Dual Active Phase Shift Full-Bridge (DAB-PS) Zero Voltage Switching (ZVS) converter, the introduction and partial description of which can be found in Part II.
In this section, we’ll describe some of the DC-DC-level design processes that our engineering team follows. Specifically, we explain the key design considerations and trade-offs in developing such a converter, especially around the definition of magnetic components, and discuss power supply simulation and design decisions made. In part 4, we will also discuss the concept of flux balancing in transformers and how to solve this problem in 25 kW fast DC charging piles.
1 Design DAB DC-DC stage
The DAB DC-DC converter consists of two full bridges implemented using four SiC MOSFET modules, a resonant transformer and a resonant Inductor. The system operates phase-shift modulation and achieves ZVS at high loads while maximizing efficiency over a wide output voltage range of 200 V to 1000 V. Figure 1 again shows the simplified schematic of this circuit stage previously introduced in the second part.
The converter is designed to provide the highest efficiency when the output voltage is between about 650 V and 800 V. For charging stations for 400 V batteries, the design should be adjusted to provide peak efficiency around the 400 V level.
Table 1 summarizes the main design features of this converter.
Figure 1: A dual active bridge (DAB) DC-DC stage consists of two full bridges with an isolation transformer in between.
Table 1. Overview of required operating points for DC-DC converters.
DAB Magnetics Design Guide
A fundamental step in designing a DAB-PS converter is to select the key parameters of the transformer and resonant inductor. The transformer turns ratio (n1/n2) will significantly affect the efficiency of the converter over the entire operating range, so the development and optimization of a DAB-PS converter is highly dependent on the magnetics.
As will be discussed below, most simulation targets are only used to generate magnetic performance requirements that meet the needs of our application. Magnetic component suppliers use this information to design and manufacture components that meet application needs while minimizing losses and size.
Transformer turns ratio (n1/n2) and efficiency
When the secondary voltage (VSEC) equals the primary voltage multiplied by the n1/n2 ratio (Equation 1, the DAB-PS converter will reach peak efficiency.
Therefore, adjust the transformer in such a way that when VSECThis peak performance operating point is reached at the target output voltage (approximately 650 V to 800 V for this project). The following simulations will show how the turns ratio can be a major determinant of converter efficiency (for a fixed switching frequency and switching technique) as it affects the transformer’s primary (IPRIM,RMSand IPRIM,PEAK) current and secondary (ISEC,RMSand ISEC, PEAK) current. Simulation will help determine which turns configuration will improve the overall efficiency and achieve the target value of 98%.
In order to get the simulation up and running, some initial values for the transformer turns ratio are required. In this project, initial values are proposed based on experience gathered from previous designs, market benchmarks, and technical literature, with Equation 1 as a solid foundation.
Resonant inductance (LRESONANT)
The resonant inductance value needs to be adjusted according to the leakage inductance of the transformer in the DAB-PS. Theoretically, in some designs, the inherent leakage inductance of the transformer can be used to achieve the necessary resonance to support ZVS. However, in high power applications like this project, this is not the case, so the value of the resonant inductance chosen needs to complement the leakage inductance of the transformer.
Equation 2 defines the relationship between the DAB-PS converter’s output power, primary and secondary voltages, switching frequency, phase shift, and resonant inductance (resonant inductance + transformer leakage inductance). Based on typical situations in power converters, it has been shown that fsThe higher the value, the less inductance is required.
where P is the power transfer of DAB, VPRIMis the primary voltage, VSECis the secondary voltage, ɣ is the phase shift, fsis the switching frequency, LRESONANT+LEAKAGEis the resonant inductance + transformer leakage inductance. This formula is based on a simplified linearized model, but is useful for initial estimates.
By applying Equation 2 and comparing it to the specification of a 25 kW DC charger, it can be determined that LRESONANTwith LLEAKA value of around 22 µH would be a reasonable assumption. Table 2 shows that for the worst case (VSEC = 200 V), a rated output power of 10 kW can be provided with some margin, since the ideal maximum power transfer is 11.57 kW from a resonance point of view.
Table 2. L required to meet output power specifications over the entire output voltage rangeRESONANT+LEAK.
Excitation inductance (LM)
Excitation inductance (LM) plays an important role in optimizing transformer size and also affects overall efficiency. For a given primary voltage, higher LMwill translate into lower excitation current (IM), thereby reducing the total magnetic flux through the core and reducing the required effective cross-sectional area (Ae) (Equations 3, 4, and 5), which would make the transformer more compact.
Nevertheless, higher LMvalue implies an increase in the number of turns (n1) required, which in systems operating at high RMS currents (such as the 25 kW EV charger design in this example) results in an increase in the cross-sectional area of the conductors (to allow conduction losses are controlled), which then leads to an increase in the size of the transformer to be able to accommodate the core in the available winding area of the core.
Clearly, the magnetizing inductance value is an element of transformer design and optimization, but not a fixed requirement for our converters. So the approach our engineers have taken here is to rely on the magnetics manufacturer to provide an optimized design that is as compact and efficient as possible while meeting the application requirements (primarily efficiency, size and cost). However, Equations 3 to 5 help us understand how magnetizing inductance affects the terms that change transformer size and losses.
where B is the magnetic flux density, φ is the magnetic flux, and Aeis the effective cross-sectional area (of the core).
where µ0is the vacuum permeability, µris the relative permeability, leis the length of the magnetic path, lais the core air gap length, N is the number of turns of the primary winding, IMis the excitation current.
where ALis the inductance coefficient.
From a control and regulation point of view, the LMIt is also important to establish a minimum value. The lower the value, the faster the control loop can run, and the acquisition and control hardware needs to support that speed.
To summarize, in this project define LMThe most important factors for an acceptable range include: maximum adjustment speed,MInfluence of peak current, influence on secondary side current (with LMdecrease and increase) and the feasibility of the magnet structure (compact).
The switching frequency of 100 kHz was chosen based on experience gained in previous designs such as 11 kW LLC converters.This value is a trade-off between relatively high switching frequency (which helps reduce magnet size) and too high switching frequency (which results in excessive switching losses).
Phase shift method and several options
For simulation purposes, a single phase shift with a fixed 50% duty cycle is used between complementary bridges. It is planned to evaluate other phase shift methods (eg extended phase shift, dual phase shift and three phase shift) at the actual control implementation level as one of the possible means to improve system performance.
Flux balancing techniques are designed to prevent core saturation in transformers caused by so-called flux leakage. This phenomenon, also known as the flux ladder effect, is caused by the accumulation of residual flux in the magnetic core during each switching cycle due to an unbalanced net product (volts x time) applied to the transformer – in one switching cycle It should be exactly zero during the period. When the product is not zero, the applied voltage waveform is not pure AC, but contains a DC bias component that causes residual flux.
The imbalance behind the (volts x time) product can be very subtle and difficult to identify, such as the duty cycle or R of a single half-bridgeDSONitself. In small and medium power systems, a “DC blocking capacitor” is used in series with the primary or secondary winding to filter the DC bias current. In a 25 kW charging pile design, the characteristics and requirements of this capacitor can make the component bulky or impossible to implement. The capacitance value will fall in the range of tens of microfarads, and the DC blocking voltage will be around 1000 V.
However, the most challenging and restrictive is the IPRIM,RMSand ISEC,RMSVery high, expected to be somewhere between 45 A and 65 A. A suitable solution requires about 15 to 20 ceramic capacitors in parallel, which is impractical for a number of reasons, including size, cost, layout complexity, and system reliability. An alternative is to use electrolytic capacitors or metallized polypropylene capacitors, similar to those used in the DC link of the PFC stage, but this takes up a lot of space on the PCB and increases the BOM cost.
To achieve a practical, compact and competitive design, one possible solution is to prevent the magnetic flux ladder effect. This can be accomplished in a number of ways, and there is a wealth of literature on the subject. The solution implemented in this project is a flux balancing algorithm that controls and modifies the voltage wave (duty cycle) applied to the primary and secondary windings of the transformer in order to keep them balanced so that the average DC current is zero.
The primary and secondary currents are measured as inputs to the control loop, which requires additional measurement of the primary and secondary currents of the transformer, whereas for actual converter control, only the input and output currents are sensed. On the other hand, flux balancing eliminates the need for capacitors, reducing size and cost, and increasing system efficiency. These factors, along with the engineering team’s previous expertise in implementing this technology, are the main reasons for the popularity of this approach. Part five of this article series will provide more details on implementing flux balance control techniques.
2 Preparing for Simulation
In addition to discussing the development of the PFC stage, the third part of this series It also provides a broader overview of why simulation is critical in power electronics design, and the main factors to consider before running a simulation, such as goals, models, and input parameters. Keeping these factors in mind will aid in successful project development and execution. The key information for DAB-PS level power supply simulation is presented below.
The primary goal is to verify the target efficiency of the system, and thereby help select the parameters of the transformer and resonant inductor to maximize efficiency while meeting the rest of the system’s requirements. Table 3 outlines the main goals.
Table 3. Summary of the main goals of the simulation.
The SPICE power simulation model developed by the ON semiconductor engineering team for the DC-DC converter is shown in Figure 2. It is simpler than the power supply simulation model of the three-phase PFC stage presented in Part III, which switches three half-bridges and requires synchronization of AC grid currents and voltages. In the DAB-PS converter, the power stage uses four half-bridge cells (the same blocks used in the PFC model).
As for the transformer and resonant inductance, the model contains: the coupling ratio of Lpri to Lsec (K = 1), Lm (magnetizing inductance), Ls (secondary inductance), Lr (resonant inductance) and equivalent series resistance (for transformer and inductor winding). It should be emphasized that the core losses of the transformer and inductor are not included. At this stage, a feasible starting point for considering these factors is to estimate that the loss approximates the conduction loss.
Other components in the model include C_Pri and voltage current sensors (SPICE format) to measure primary and secondary currents for flux balance. C_Pri represents the snubber capacitor used at the DAB-PS input in parallel with the DC link. Such capacitors should be placed close to the MOSFET to suppress voltage spikes that appear on the switching node.
In a final product implementation, these capacitors may not be needed, or they may be much smaller in size, since the DC link portion of the PFC already provides filtering. However, for the purpose of this project, the DAB-PS should function properly as a stand-alone system for independent evaluation, so this capacitor is essential. As mentioned earlier, this control model employs a custom digital PWM model operating with a 50% single phase shift.
Figure 2: Simulation model of the DAB converter.
Tables 4 and 5 summarize the simulation input parameters. will use n1/n2, LMand VSECalternative values are evaluated and the optimal configuration is finally determined. The remaining parameters were held constant across all simulations and were chosen as a starting point based on our engineering team’s expertise in passive component design, benchmarks of existing solutions, and literature surrounding the topic.
Table 4. Simulation input parameters. Highlighted in blue are the parameters that will change in the simulation.
Table 5. Configuration for SPICE simulation.
3 Simulation results
This section discusses the results obtained from the simulation. The test can be divided into two main evaluations, the first evaluation revolves around the transformer turns ratio n1/n2 and efficiency, and the second evaluation revolves around LM. The test results will help achieve the goals presented earlier and answer key design questions. Note that all simulations are performed at the values provided in the Input Parameters section unless otherwise stated.
Transformer turns ratio (n1/n2) evaluation
Efficiency and Loss
The first and most representative results of the simulation are shown in Figures 3 and 4. Peak efficiencies are provided at secondary operating voltages of 800 V, 666.7 V, and 571 V, respectively, depending on the n1/n2 configuration. It is worth noting here that at 340 V to 830 V VSECA peak efficiency of 98% is achieved for all evaluated turns ratios over the operating voltage range (excluding inductor and transformer core losses).
However, with VSECMoving towards the low end (200 V) and high end (1000 V), the difference between the different n1/n2 ratios becomes more pronounced. Actual VSECThe farther the value deviates from the optimum point, the worse the efficiency (left and right ends of the graph in Figure 3). Interestingly, while increasing n1/n2 increases V significantlySEC > VSEC,OPTIMtotal power loss (right end of Figure 4), but reducing n1/n2 has no effect on VSEC SEC,OPTIMThe power loss at the time has an equally pronounced effect (left end of Figure 4).
Although increasing the n1/n2 ratio will make VSEC SEC,OPTIMefficiency increases (left end of Figure 3), but the difference is not as large as VSEC > VSEC,OPTIMwas as significant (right end of Figure 3). Therefore, it seems that reducing the n1/n2 ratio may lead to an increase in overall performance, although this is not always the case, depending on the overall VSECMinimum efficiency to be ensured within the scope of work.
Figure 3: With VSECVariation in DAB efficiency for different n1/n2 ratios of voltages and transformers. Core losses of resonant inductors and transformers are not included. VDC-LINK = 800 V, LM = 720 µH.
Figure 4: With VSECVariation in DAB power loss for different n1/n2 ratios of voltage and transformer. Core losses of resonant inductors and transformers are not included. VDC-LINK = 800 V, LM = 720 µH.
primary and secondary current
A low n1/n2 ratio also brings the disadvantage that it is usually necessary to find a sweet spot. The most prominent disadvantage is the low VSECtime IPRIM,PEAKand IPRIM,RMShigher (Figure 5), which means that the SiC MOSFET has a higher on-current.
At the same time, increasing n1/n2 will result in high VSEClower ISEC, PEAKand ISEC,RMS(Image 6). To avoid magnetic saturation, extra care needs to be taken in the transformer design for relatively high peak currents on the primary side.
Figure 5: IPRIM,RMSand IPRIM,PEAKas a function of transformer turns ratio (VDC-LINK = 800 V, LM = 720 µH).
Figure 6: ISEC,RMSand ISEC, PEAKas a function of secondary side voltage and transformer turns ratio (VDC-LINK = 800 V, LM = 720 µH).
Primary Voltage, Secondary Voltage and Inductor Voltage
Figure 7 depicts the voltage across the transformer windings. These are values that need to be passed to the transformer manufacturer for them to calculate the required isolation.
Figure 7: V between the two terminals of the transformerPRIM,PEAKand VSEC, PEAKVoltage as a function of secondary side voltage and transformer turns ratio (VDC-LINK = 800 V, LM = 720 µH).
Again, Figure 8 shows the voltage across the resonant inductor. In both cases, the voltage evolution follows a similar pattern, with the voltage across the two terminals increasing with VSECincreases with the increase. In all cases, the voltage value remains below 1000 V, which is not a problem for common inductors.
Figure 8: Resonant inductor voltage across terminals as a function of secondary-side voltage and transformer turns ratio (VDC-LINK = 800 V, LM = 720 µH).
Transformer magnetizing current (for a given LM) is not affected by changes in n1/n over the entire VSECSignificant variation was shown over the operating voltage range (Figure 9).
Figure 9: IMas a function of secondary side voltage and transformer turns ratio (VDC-LINK = 800 V, LM = 720 µH).
Excitation inductance (LM)Evaluate
This section describes the effect of different magnetizing inductance values on system performance. Note that we performed three simulation series with different magnetizing inductances (720 μH, 300 μH, and 150 μH). In this analysis, the n1/n2 of the transformer has been fixed to 1.2:1.
In the previous chapter, a relatively high L has been usedmA fixed value (720 μH), the effect of turns ratio (n1/n2) on efficiency and other variables was evaluated. As shown in Figure 9, this choice results in a maximum IM, PEAKBelow 5 A, which seems to be in line with a common rule of thumb in power transformer design, which is to design the transformer toM, PEAKThe value of is approximately the maximum IPRIM,PEAK(82 Apeak in Figure 5) at 5% to 10%.
Figure 10 shows LMThe actual effect on efficiency is very low, at very high VSECThe bottom shows only a 0.4% difference. As mentioned in the section “DAB Magnetics Design Guidelines”, the actual value of the magnetizing inductance is not a critical requirement of the project, but is chosen by the magnetics supplier in order to make the transformer as compact as possible while meeting the remaining requirements.
Figure 10: VDC-LINK = 800 V, DAB efficiency and power loss as a function of secondary-side voltage and magnetizing inductance for n1/n2 = 1.2:1. Core losses of resonant inductors and transformers are not included.
Another revelation from the simulation is that at different LMvalue, IPRIM,PEAKand IPRIM,RMSremained almost unchanged (Figure 11). However, this is not the case on the secondary side (Fig. 12), at different LMvalue, ISEC, PEAKand ISEC,RMSJumped from 91 Apeak to 109.6 Apeak and jumped from 49 Arms to 58.7 Arms, respectively.
From this observation and further research, we can understand how magnetizing inductance affects transformer size. ISEC,RMSincreased by a factor of 1.435 (LM = 150 µH (58.7 Arms) vs. LM= 720 µH (49 Arms)), which can be explained by the need to increase the cross-sectional area of the wire by the same factor (if the winding losses remain the same). However, n2(LM= 150 µH) to 1/2.19, using the same winding cross-sectional area will reduce copper losses to 1/1.52. On top of that, n1 (the number of primary turns) is also reduced, further reducing copper losses.
Still, this improvement may come at the cost of larger cores. With LMdecrease, IM, PEAKincreased by a factor of 4.8, from 4.1 A(LM = 720 µH) to 19.9 A (LM = 150 µH), as shown in Figure 13, while n1 (and n2) are only reduced to 1/2.19 (as described above). Applying Equation 3, the product N · IMincreases, the magnetic flux density (B) increases, which triggers theecross-sectional area) in order to maintain a reasonable level of magnetic flux density (B).
This example illustrates how these elements are related and why tradeoffs are often made. However, find the transformer size and LMThe sweet spot in between usually depends on the skill and capability of the magnetics designer (as mentioned earlier).
Figure 11: DAB IPRIM,PEAKand IPRIM,RMSVariation as a function of secondary-side voltage and magnetizing inductance (VDC-LINK = 800 V, n1/n2 = 1.2:1).
Figure 12: DAB ISEC, PEAKand ISEC,RMSVariation as a function of secondary-side voltage and magnetizing inductance (VDC-LINK = 800 V, n1/n2 = 1.2:1).
Figure 13: DAB IM, PEAKVariation RMS as a function of secondary-side voltage and magnetizing inductance (VDC-LINK = 800 V, n1/n2 = 1.2:1).
4 Conclusions and Design Tradeoffs
The simulations presented in the previous sections were used to verify the initial goals of the DAB converter and to help make design decisions, especially those involving transformers and resonant inductors. Tables 6 and 7 show the final selection of parameter values for the system. These values are passed on to the magnetics manufacturer for them to develop optimized magnetics.
The transformer turns ratio n1/n2 has been set to 1.2:1.0 as this configuration shows the best performance over the entire operating range, at VSEC = 800 V exhibits high peak efficiency (99.4%) at VSEC = 99% at 900 V, while exhibiting only a small drop in efficiency near the low side (200 V) and high side (1000 V) (Figure 3) compared to other turns ratios (1.4:1.0 and 1.0:1.0 ) performs better.
The requirements for the LM are more flexible, with ratings ranging from approximately 150 µH to 300 µH. This value is a compromise of many factors mentioned in the DAB Magnetics Design Guidelines. in IM = 20 A (and below), a minimum L should be ensuredMValues are 150 µH, while ranges up to 300 µH leave L for magnetics manufacturersMvalue to provide the most compact and efficient overall transformer design possible.
10 µH was chosen as an estimate of the resonant inductance based on the recommendations in the DAB Magnetics Design Guidelines section.
Last but not least, the equivalent series resistance (ESR) value of the transformer and inductor has been proposed as the maximum reasonable estimate that conforms to other defined parameters. It goes without saying that the lower the resistance value is in the actual magnetic design, the better. This is an optimization process that magnetic component suppliers can add value to.
Table 6. Design parameters selected for the transformer. These are used to specify transformer requirements for transformer manufacturers.
Table 7. Design parameters selected for resonant inductors. These are used to specify inductance requirements for transformer manufacturers.
The next step in the development process will be to share requirements with magnetic component manufacturers and receive design proposals for magnetic components. Once samples of the magnetic components are obtained, their actual parameters can be measured and new simulations run with the improved parameters in the SPICE model. A second analysis is performed before the actual converter hardware is obtained, providing more accurate performance and loss results.
For example, core losses can be added to the simulation because magnetic manufacturers usually provide actual values. While magnetic parameters will be discussed in the next article in the series, actual measured magnetic parameters will also help enhance the control model and help advance the development of control algorithms and control loops before hardware is available. This helps speed up the development process, as using high-level models may simplify debugging and tuning the hardware.
Stay tuned for the next article in the series, Part 5, which discusses control algorithms and implementation guidelines for control loops.